Hi,
I'm Choi.
I use E3845's MIPI interface for camera interface.
I measured the receiving latency of E3845 MIPI Interface.
The measure step is as follows,
1. With FPGA via D-PHY IC, I send image frame(640 x 480 x 16bit, with 2 lane D-Phy)
2. I set a GPIO pin high at FPGA side just after completion of each image frame transmission.
(The GPIO pin return to low state after tens of micro seconds.)
3. CPU's ISP receives the frame successfully and saves the frame on DDR memory.
4. CPU set a GPIO pin high, (One of CPU's GPIO pin)
5. I check the interval FPGA GPIO pin's rising point to CPU GPIO pin's rising point.
The received frame was perfect. There was no Checksum error or sequence Number error.
And with viewer program, the received image look same as the source image.
D-PHY IC has just small size buffer.
CPU's application was developed with WindRiver Linux 7.x.
I know WR Linux didn't support pre-emptive RT for MIPI ISP.
So, we raised the task's priority to the highest level as high as possible to reduce the latency.
Now, my question is this,
I expected the the latency is below 1 msec,
But, the latency was over 3 msec.
The latency is disappointingly long.
Why the latency is so long ?
Does the ISP use PCIe bus internally ?
Or there are 2 step buffering ?
Isn't there any know-how to reduce the latency dramatically under 1 msec ?
Regard,
Choi
