Hello,
in my design with I211 it looks like the iNVM security lock can not be activated.
The eeupdate tool always reports that the iNVM is not locked (/INVMISLOCKED option), although the INVM contains the special 'lock setting' (bit15 set in iNVM word 0x0A).
The iNVM was programmed with a MAC address and the standard Intel "I211_Invm_NoAPM_v0.6.txt" but with:
WALD 0x0a = 0xC02F PCIE_RST ; [Intel] Set GPAR_EN + iNVM LOCKED
The contents of the iNVM read back through the PCIe BAR0 are correct:
12120: 19 00 00 15 19 02 BA FF - 19 04 DA 02 02 00 E8 16
12130: 41 15 00 00 02 00 8D 03 - 21 3C 40 0B 11 14 2F C0
12140: 11 36 00 34 11 1A 39 15 - 11 42 84 05 11 48 80 02
12150: 19 1E 43 73 1A 00 00 00 - 41 02 10 08 02 00 D1 16
12160: A8 00 FF 00 02 00 D0 16 - 90 00 00 5E 00 00 00 00
12170: 00 00 00 00 00 00 00 00 - 00 00 00 00 00 00 00 00
12180: 00 00 00 00 00 00 00 00 - 00 00 00 00 00 00 00 00
12190: 00 00 00 00 00 00 00 00 - 00 00 00 00 00 00 00 00
121A0: 00 00 00 00 00 00 00 00 - 00 00 00 00 00 00 00 00
121B0: 00 00 00 00 00 00 00 00 - 00 00 00 00 00 00 00 00
121C0: 00 00 00 00 00 00 00 00 - 00 00 00 00 00 00 00 00
121D0: 00 00 00 00 00 00 00 00 - 00 00 00 00 00 00 00 00
121E0: 00 00 00 00 00 00 00 00 - 00 00 00 00 00 00 00 00
121F0: 00 00 00 00 00 00 00 00 - 00 00 00 00 00 00 00 00
12200: 00 00 00 00 00 00 00 00 - 00 00 00 00 00 00 00 00
12210: 00 00 00 00 30 00 00 01 - 81 84 88 46 A0 52 B2 48
Pin12 (SECURITY_EN) is pulled up to 3.3V with 10k, nothing else connected. According to the documentation this pin is sampled at the rising edge of LAN_PWR_GOOD, which is connected to the powergood signal of the 3v3 supply. I verified with the oscilloscope that Pin12 is already high when the rising edge on LAN_PWR_GOOD occurs, so the "invm security" should be enabled.
The only thing I notice is that after approx 30ms, the Pin12 is driven low by the I211 (probably used for NVM_SI?), and the pin is still low when PE_RST_N deasserts. So in case that the I211 would also sample the pin level when the PCIe reset goes away, it could explain why I can't enable the iNVM Lock.
How does the EEUPDATE program determines the iNVM locked state ? I can't find any register where the actual locked state can be read from.
Any help appreciated,
thanks,
Jon