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Xeon D Power Sequence Issue

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Hi,

 

We are trying to bringup a new PCB, based on the Power sequence described in BDW_DE_SoC_EDS_vol3._544042_R2_1.pdf.
Judging by the SOC outputs, sequence is proceeding correctly nearly till the end (we see SOC de-asserting SLP_S4_N and SLP_S3_N, asserts DRAM_PWR_OK, activates clocks, ands read from SPI bus).
However for some reason PROCPWRGD_PCH and PLTRST_N never go inactive.
We checked several critical outputs from CPU (such as CATERR_N, FIVR_FAULT). but all seem to be ok.
Can anyone advise how to root cause the reason why PROCPWRGD_PCH is not deasserted by the SOC? e.g. which signals to check?

Thanks,

Izak Nashelsky


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