We have a Xeon 1539 10Gb KR connected via backplane to a Kintex Ultrascale (KU115) FPGA and are having data quality issues when sending from the Xeon to the FPGA. There are a lot of bit errors when transmitting known patters via UDP.
FEC is off; auto-neg and link training are on although there is some question as to whether the FPGA performs any analysis of the training data and just indicates the link is OK.
We have eye diagrams from the FPGA receive side that indicate a poor quality connection.
Are there any registers where we can tweak the power level (or other parameters) on the Xeon transmit side? I ask here because Xeon D1500 data sheet seems to be missing the integrated PHY registers(?). (Section 3.8.1 links to appendix B and appendix B(B.5) links to section 3.8.1)