I'm trying to get Coreboot and FSP working on the Cougar Canyon 2 Customer Reference Board (CRB). I followed the instructions given at www.intel.com/fsp within the PDF document: "3rd Generation Intel® Core™ Processor with Mobile Intel® HM76/QM77 Express Chipset Customer Reference Board: Platform Guide". I can build and flash coreboot (coreboot.rom) successfully, but SeaBIOS fails start. The problem is that the board keeps rebooting before the payload runs.
I've listed the console output below. I'm new to Coreboot/FSP so I'm not up-to-speed on how to debug this issue. But since the document is well written and there is lots of references in the code (and on Intel websites) for Coreboot/FSP on the Cougar Canyon 2, I'm surprised that this doesn't work "out of the box" so to speak. I'm curious to know if anyone else has gotten this to to work, and If so, can you please reply with some pointers on what I may be doing wrong?
Thank you,
- Jerry
<< Coreboot console output >>
coreboot-4.1-166-g9c1b33e Thu Jul 30 03:21:28 UTC 2015 romstage starting...
POST: 0x41
POST: 0x42
Setting up static southbridge registers... done.
Disabling Watchdog reboot... done.
done.
POST: 0x43
Setting up static northbridge registers... done.
Back from sandybridge_early_initialization()
POST: 0x44
ME: FW Partition Table : OK
ME: Bringup Loader Failure : NO
ME: Firmware Init Complete : NO
ME: Manufacturing Mode : NO
ME: Boot Options Present : NO
ME: Update In Progress : NO
ME: Current Working State : Reset
ME: Current Operation State : Preboot
ME: Current Operation Mode : Normal
ME: Error Code : No Error
ME: Progress Phase : ROM Phase
ME: Power Management Event : Clean Moff->Mx wake
ME: Progress Phase State : BEGIN
Intel ME early init
Intel ME firmware is ready
ME: Requested 16MB UMA
POST: 0x45
POST: 0x46
POST: 0x48
Starting the Intel FSP (early_init)
POST: 0x49
FSP Version 1.8.0 Build 0
FSP Status: 0x0
ME: Sending Init Done with status: 0, UMA base: 0x0ff0
ME: Requested BIOS Action: Continue to boot
ME: FW Partition Table : OK
ME: Bringup Loader Failure : NO
ME: Firmware Init Complete : NO
ME: Manufacturing Mode : NO
ME: Boot Options Present : NO
ME: Update In Progress : NO
ME: Current Working State : Normal
ME: Current Operation State : Bring up
ME: Current Operation Mode : Normal
ME: Error Code : No Error
ME: Progress Phase : BUP Phase
ME: Power Management Event : Pseudo-global reset
ME: Progress Phase State : 0x2c
FD & FD2 Settings:
PCI Bridge (D30:F0) Disabled
SATA 1(D31:F2) enabled
SMBus Config space enabled
High Definition Audio Disabled
Reserved bit 5 set
Reserved bit 6 set
Reserved bit 7 set
Reserved bit 8 set
Reserved bit 9 set
Reserved bit 10 set
Reserved bit 11 set
Reserved bit 12 set
EHCI #2 Enabled
LPC Bridge Enabled
EHCI #1 Enabled
PCIe bridge 1 Disabled
PCIe bridge 2 Disabled
PCIe bridge 3 Disabled
PCIe bridge 4 Disabled
PCIe bridge 5 Disabled
PCIe bridge 6 Disabled
PCIe bridge 7 Disabled
PCIe bridge 8 Disabled
Thermal Sensor (D31:F6) Registers Enabled
SATA 2 (D31:F5) Disabled
Reserved bit 26 set
Reserved bit 28 set
Display BDF Enabled
MEI #1 (D22:F0) Enabled
MEI #2 (D22:F1) Enabled
IDE-R (D22:F2) Enabled
KT (D22:F3) Enabled
memcfg DDR3 clock 1333 MHz
memcfg channel assignment: A: 0, B 1, C 2
memcfg channel[0] config (03600008):
ECC active
enhanced interleave mode on
rank interleave on
DIMMA 2048 MB width x8 single rank, selected
DIMMB 0 MB width x8 single rank
memcfg channel[1] config (03600008):
ECC active
enhanced interleave mode on
rank interleave on
DIMMA 2048 MB width x8 single rank, selected
DIMMB 0 MB width x8 single rank
POST: 0x4b
POST: 0x4c
POST: 0x4d
POST: 0x4e
CBMEM:
IMD: root @ badff000 254 entries.
IMD: root @ badfec00 62 entries.
<< reset / repeat >>