The Intel Xeon Phi coprocessor, the first product of Intel’s Many Integrated Core (MIC) Architecture, is a new accelerator technology developed by Intel to enable performance gains for highly parallel computing workloads. It possesses several interesting and appealing features, including the ability to use familiar programming models such as OpenMP and MPI.
The Intel Xeon Phi Coprocessor Workshop, offered by Universidade Estadual Paulista (UNESP) in partnership with Intel Software do Brasil, aims to provide a comprehensive, practical introduction to the Xeon Phi architecture and programming models. It has been conceived with a special focus on the active participation of the attendees.
The first day provides a general introduction to the Intel Xeon Phi coprocessor. Participants will learn about the architecture, software infrastructure, supported programming models, and OpenMP and MPI programming and analysis.
The second day builds on information learned during the first day and provides practical coverage with hands-on activities. Participants will work on predefined sets of exercises that address a wide range of aspects aimed to help them get more familiar with the Intel Xeon Phi coprocessor architecture.
This event is sponsored by:
