82580 Transceiver 4 ports set to different types of interfaces
Hello,I'd like to set port 1 on my 82580 in 1000base-BX mode and the remaining 3 ports in SGMII mode. In my current hardware, I have wired the LAN0 MDC/MDIO lines to the PHYs. LAN0 is a 1000 base BX...
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White Paper: Why Dissimilar Redundant Architectures Are a Necessity for DAL A
For avionics systems requiring DAL A certification, adhering to the required <1 in 10-9 probability of failure is no easy feat. Take, for example, a flight control computer that relies on multiple...
View ArticleHow to set config/mac data to Springville I210IT?
We use a Apollo lake(APL) SOC , which connect to the intel Ethernet chipset -Springville I210IT.In order to enable the Ethernet function, our understanding is some configuration data(e.g.: vender id,...
View ArticleHSUART support in Coreboot
Hi, We are developing a coreboot image for Apollo lake custom board. We would like to have the coreboot boot-up on serial console.We are having HSUART ports in our custom board and we would like to...
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PLEVT SATA margin test
Hello, Our DQA member tries to SATA margin test on Denventon platform they used #526691(Intel Physical Layer Electrical Validation Tool Ver 1.12.7) But the Tool can't capture SATA data that like below...
View ArticleUpgrading Apollo Lake to 16GB DDR3L memory -40 to 95°C with DRAM from...
Intels Apollo Lake CPUs can take up to 16GB DDR3L RAM at 1866MT/s speed in Non-ECC operation.Optionally ECC can be used with reduced maximum operation speed of 1600MT/s. These 16GB need to be split...
View ArticleEEUPDATE and LANConf Guide
Hi Intel Embedded Community: We will use the tools EEUPDATE and LANConf (from the Quartzville tools package) for programming the MAC in a i211. Could you please provide us the usage guide for this...
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max10 on chip flash write issue (without nios)
max10 on chip flash write issue (without nios) hi, can anyone help to answer this question? I am trying to write data to max10 on chip flash(UFM) without using NIOS.what i am doing is to write a...
View Article[pktgen-dpdk]Only can send a few packets and stopped.
When I run pktgen-dpdk on computer A and run dpdk on computer B, the pktgen can only send a few packets( about one second) and stopped.The command on A side is ./tools/pktgen-run.sh.I modified some...
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Which intel tech document for IOC and SOC communication in boot up?
hi, We worked on MRB intel reference board, which has Apollo lake SOC mounted, and another IOC module.We understand during boot up phase, IOC will send some commands to the bootloader, which is running...
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How to connect four xl710 to one x557
Hello, we want configuration is shown in Figure. Connect the xl710 to four different CPU and connect to a 4port x557(X557-AT4) we could't find this contents in datasheet or reference schematics. Is it...
View ArticleCPLD consumption
Hi, I'm using a 5M570ZT144C5N CPLD to light 100 LEDs. Each LED is connected in a IO pin. Each LED need 10mA. That is to say each pin pass 10mA.If all the LEDs are lighted at the same time, I have more...
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How to configure Linux SPI driver mcp251x?
Hello, I use an Intel Atom processor E3930 with CAN controller MCP2515 with SPI interface. In the Linux kernel there is a driver "drivers/net/can/spi/mcp251x.c". I am only famiiliar with Linux device...
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Curtiss-Wright and Green Hills Software Demonstrate INTEGRITY-178 tuMP...
Intel® Quad-Core Xeon® processor-based VPX3-1220 RTCA/DO-254 safety-certifiable COTS SBC supports Green Hills Software RTCA/DO-178B Level A certifiable multi-core RTOS ASHBURN, Va. – August 14, 2018...
View ArticleMTBF for Intel CPUs
Hi, Would anybody help me to find the MTBF or FIT reliability information for the following Intel parts? FH8065301487717 SR1X6 CPULH8066803102601 SR33P CPU10M02SCU169I7G FPGA Thank you very much! John
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Where is the Intel/Altera FPGA section of the forums?
Hi all. Is there an area of the forum on the subject of Intel Altera FPGAs, and all things FPGA related? I am used to the layout of the Altera forum boards and i seem to be having trouble navigating...
View ArticleE3930 PCIe memory access issues
Hi, the tested E3930 SoC (microcode: sig=0x506c9, pf=0x1, revision=0x2c) has issues accessing the 32-bit non-prefetchable memory resource of Xilinx PCIe Endpoint (Vendor 10EE Device 0007). Within each...
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Application/algorithm efficiency - MIPS versus DMIPS
Dear all, We are trying to have a rough comparison measure of efficiency of a set of algorithms running across different CPU architectures and trying to understand how we can express it in an...
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Live mobile video & IoT sensor monitoring for First Responders
FirstNet certified, enabling Fire, Police & Paramedics, LiveCast’s solutions are used for in variety of mission critical situations every day. Wireless, mobile video solutions are transforming the...
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Broadwell-DE No MDC/MDIO
Hi, Problem: No MDC/MDIO signalCPU: Broadwell-DE SoC, 4Core/8T10G BASE –T PHY: Intel, X557-ATFlash Image:1. BDXDE_KR_BACKPLANE_LED_LO_NO_MNG_1.13v02_800006D1.bin2....
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